Backside Power Delivery Network Integration in Physical Design
Three rival foundry approaches reshape chip design at the physical layout stage.
Priya Subramaniam
Senior Technical Editor
Priya spent a decade as a physical design engineer at two major semiconductor IP companies before turning to technical journalism in 2014. She covers the full physical design flow with particular depth in place-and-route methodologies and advanced node process constraints.
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Three rival foundry approaches reshape chip design at the physical layout stage.