A blog and newsletter on Backend physical design workflows and Self-learning and cognitive AI agents in EDA and chip implementation.
- Die-to-Die Interface Physical Implementation for UCIe Compliant DesignsThe hard physical constraints that make multi-vendor chiplet interoperability actually work.Tobias Mwangi · 10 min read
- POCV vs AOCV Derating in Timing Sign-OffWhy a design choice between three derating methods matters at advanced nodes.Yeonok Hwang · 9 min read
- Backside Power Delivery Network Integration in Physical DesignThree rival foundry approaches reshape chip design at the physical layout stage.Priya Subramaniam · 11 min read